Processing systems include memory systems configured to store data, instructions, etc. A memory, such as a cache associated with a processor, may include a data array, for example. For an access operation (e.g., read/write), the data array may be accessed and a search may be performed to determine whether any line of the data array holds the data desired by the processor. The data may be organized in a variety of ways known in the art (e.g., direct mapped, set associative, etc.).
Searching for desired data in the cache may involve obtaining an index from an access address (e.g., one or more bits of the address associated with the access operation) and searching a location in the cache corresponding to the index to determine if the cache holds data corresponding to the address. For example, a tag array may hold tags comprising at least a portion of the addresses corresponding to data stored therein and searching the cache may involve comparing (e.g., for a bitwise match) bits of the access address and the tag at the indexed location. If there is a match, then a cache hit is determined and data may be read out from the indexed location.
The bitwise comparisons for determining whether there is a match can involve reading out the bits of the tag (or, more generally, a stored line), and then comparing each bit read out with a corresponding bit of the access address (or, more generally, a search word). The results of the bitwise comparisons, i.e., match or mismatch, for each bit may then be aggregated with the results of the comparisons across all the bits to determine the overall hit/miss or match/mismatch indication of the search word with the stored line.
In conventional memory access operations which involve a search, the above-mentioned steps, i.e., a bitwise read, followed by a bitwise compare, followed by aggregation across a plurality of all bits of the stored line, are serialized. Therefore the search can involve significant delays. With ever increasing demands for high performance computing, there is a need for improved memory access speeds, and a corresponding need for reducing the delays involved in the conventional search operations.